The present invention relates to reconfigurable integrated circuits. More specifically, it relates to a highly economical single IC that holds multiple fully optimized ASIC design partitions, each partition utilizing the entire IC. The user can switch between partitions quickly, without incurring delays to reconfigure configuration memory.
Traditionally, integrated circuit (IC) devices such as custom, semi-custom, or application specific integrated circuit (ASIC) devices have been used in electronic products to reduce cost, enhance performance or meet space constraints. However, the design and fabrication of custom or semi-custom ICs can be time consuming and expensive. The customization involves a lengthy design cycle during the product definition phase and high Non Recurring Engineering (NRE) costs during manufacturing phase. Further, should design errors exist in the custom or semi-custom ICs, the design/fabrication cycle has to be repeated, further aggravating the time to market and engineering cost. As a result, ASICs serve only specific high volume and low cost applications. Each ASIC comprises a customized interconnect structure that mandates a unique construction for a specific application. If multiple applications are designed to share a single IC, the ASIC foot-print has to grow to incorporate multiple designs into one larger design, thus increasing the cost and complexity of the IC.
Another type of semi custom device called a Gate Array customizes wiring for pre arranged modular logic blocks at a lower NRE cost by synthesizing the design using a software model similar to the ASIC. The absence of silicon level design verification results in multiple spins and lengthy design iterations. A more recent trend in ICs named Array ASICs offer larger pre arranged modular blocks for the user to customize compared to a Gate Array. Larger blocks are easier to route. They both involve a customized interconnect pattern, and useful only for a single application. Similar to ASICs, a larger Array IC foot-print is needed to incorporate multiple design applications in a single IC. Larger designs are slower, more difficult on timing convergence, and takes longer to place and route.
In recent years there has been a move away from custom or semi-custom ICs towards field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user “in the field” prior to use. Off the shelf, generic Programmable Logic Device (PLD) or Field Programmable Gate Array (FPGA) products greatly simplify the design cycle. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to optimize silicon performance. The flexibility of this programmability is expensive in terms of silicon real estate, but reduces design cycle and upfront NRE cost to the designer.
FPGAs offer the advantages of low non-recurring engineering costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes), and low risk since designs can be easily amended late in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the more traditional approaches. However, the conversion from an FPGA implementation to an ASIC implementation typically requires a complete redesign. Such redesign is undesirable in that the FPGA design effort is wasted.
Compared to PLD and FPGA, an ASIC has hard-wired logic connections, identified during the chip design phase, and need no configuration memory cells. This is a large chip area and cost saving for the ASIC. Smaller ASIC die sizes lead to better performance. A full custom ASIC also has customized logic functions which take less gate counts compared to PLD and FPGA configurations of the same functions. Thus, an ASIC is significantly smaller, faster, cheaper and more reliable than an equivalent gate-count PLD or FPGA. The trade-off is between time-to-market (PLD and FPGA advantage) versus low cost and better reliability (ASIC advantage).
There is no convenient migration path from a PLD or FPGA used as a design verification and prototyping vehicle to the lower die size ASIC. All of the SRAM or Anti-fuse configuration bits and programming circuitry has no value to the ASIC. Programmable module removal from the PLD or FPGA and the ensuing layout and design customization is time consuming with severe timing variations from the original design.
One FPGA can implement multiple logic designs. Each design is identified by a bit-map pattern that specifies how all the internal programmable logic elements are to be arranged to fit the design in the FPGA. These bits are stored on-chip as configuration memory. To switch between applications, the entire bit pattern or intelligently identified portion of the bit pattern must be changed. For non-volatile configuration memory (such as EPROM, EEPROM, Flash), these erase, re-program & verify cycles are very time consuming. For volatile memory (such as SRAM) a duplicate non-volatile memory must exist outside of the chip to load the desired pattern during power up, and to change it to the new pattern when desired. That too is time consuming as chip to chip data bandwidth limitations and system processor loading hinder the action. Duplicating the configuration memory content to hold two patterns adds to the foot-print of the already expensive FPGA. Hence only single applications are implemented in production on FPGAs today.